The conventional PCB design process consists of two steps: (1) using a schematic editor to graphically draw the connectivity of the components, and (2) completing the physical layout using tools such as PADS or Eagle PCB.
PHDL is designed to replace only step one (left) above by providing an HDL (hardware description language) based tool to increase designer productivity for doing the initial design entry. The result of creating and then compiling a PHDL design is a netlist which is then imported into the physical design tool for the physical layout step.
PHDL was created because we believe that graphical schematic capture is a terribly inefficient way to do initial PC board design entry. This is partly because of the the use of high pin-count devices and wide signal busses in modern PC board design, requiring schematics to be spread across many pages. Doing so largely eliminates much of designer's ability to visually see and verify connectivity (which has always been the claimed advantage of graphical design tools for PCB's). That is, flipping between multiple pages of schematics to verify connectivity between device pins really has no advantage over flipping between multiple pages of HDL code to verify connectivity between device pins. In fact, it may have a disadvantage since the latter can be done using a text editor or software development IDE such as Eclipse rather than a graphical tool!
Furthermore, graphical schematic capture tools are usually proprietary, non-portable, and rely on closed file formats to represent the user's design. Finally, they lack all of the productivity-improving features that have made HDL's the method of choice for the design of IC's and FPGA-based digital designs over the past 30+ years.