Example Reference Design - PTZ LANC Controller

This page describes a more realistic design captured with PHDL. The design uses an FPGA for programmable logic resources, and has a wide range of devices found on a typical PCB. Some of these include: a variety of tantalum and ceramic surface mount capacitors, surface mount resistors, Flat-pack ICs, MOSFETs, LEDs, buttons, switches, and a variety of through-hole connectors. The block diagram below shows the architecture of the completed board on the right. The hatch mark with the number next to it indicates the number of I/O lines from the FPGA to the device. For example, there are two serial ports, each with a TX and RX line, so there are a total of four I/O lines required.

Click for hi-res version.

Project Background

  • What is a PTZ LANC Controller?

    PTZ Stands for Pan-Tilt-Zoom. LANC is a bi-directional serial data transmission protocol developed by Sony to interchange commands and status information between a video or still camera and an external remote control apparatus. After appropriate robotics are added to a camera tripod (or similar arrangement), accompanying electronics can be devised to position a relatively inexpensive camera to within a high degree of accuracy using off-the-shelf electronic components. This example design fulfills the electronic control portion of such a precision robotic camera application, but more importantly illustrates how PHDL can been used to capture connectivity of a PCB with a modest degree of complexity.

  • How is the design implemented in FPGA resources?

    A Xilinx Spartan3 400K FPGA was chosen to provide the programmable logic resources required to manage position, zoom and other camera specific settings in real time. The FPGA implements multi-axis precision motion controllers, each consisting of a programmable Proportional-Integral-Differential (PID) filter, an internal trapezoidal motion profile generator, and a high-resolution quadrature encoder feedback path (1000+ counts-per-revolution of the motor shaft). Each axis controller is implemented inside the FPGA with a dedicated PicoBlaze processor. The processor core and surrounding dedicated hardware replicate all of the functionality described in National Semiconductor's (now TI) LM628/LM629 family of precision motion controllers. Trajectory calculations of position, velocity, accelleration, and breakpoints are maintained to 32-bits internally, even though the PicoBlaze is an 8-bit architecture. The design was optimized for area, so 32-bit operations were scheduled accordingly on the 8-bit processor. The core is written in VHDL and PicoBlaze assembly, and can be adapted to almost any precision motion control application where a PID feedback loop is desired. This includes PWM or DAC output (serial or parallel), brushed or brushless motors. The board has motor drive amplification circuitry for both brushed and brushless motors.

  • Why use an 8-bit processor for 32-bit operations?

    A number of processor architectures were researched before embarking on this project. In the end, the PicoBlaze won due to the extremely small implementation size (less than 100 slices on average), and the highly predictable instruction and interrupt execution time. Also, controlling a motor requires real-time granularity that a MicroBlaze processor simply cannot provide. Since motor sample rates tend to be low in most precision motion applications (less than 10KHz), a small 8-bit processor running at speeds in excess of 50MHz is more than adequate to perform all arithmetic with a dedicated 16x16 multiplier and partial product multiplication, since the multiplier is readily available in modern FPGA resources. Thus, a more modular and self-contained small processor was desired over a larger single processor controlling all aspects simultaneously. This makes the RTL code more portable to FPGA's with smaller resources, and allows additional control axes to be added on an instance-by-instance basis. In terms execution times, a single divide instruction required every motor sample period completes in roughly 200 clock cycles using five iterations of the reciprocal multiplication algorithm. The processor spends most of the remaining 5,000 cycles of a motor sample period waiting and responding to requests from the controlling host application.

    Due to these chosen tradeoffs in the area-time design space, the core and accompanying surrounding hardware (quadrature decoders, dedicated registers, pwm and brushless driver circuitry) all fit in less than 300 slices for each axis. The total design including packet router to host consumes less than 1000 slices, leaving the Spartan3 400K 15% utilized. Those interested in pursuing this design or a similar one of their own may choose to implement the motion controllers in C with a MicroBlaze instead. FPGA utilization, performance benchmarks, and other statistical metrics under the MircroBlaze architecture would be welcomed for comparison purposes.

  • How are commands issued to the board?

    A host application written in C# is used to issue commands as well as poll the status of the camera. A simple variable length CRC packet protocol was designed specifically for transmitting and receiving commands over a single pair of CAT5 wires over long distance (in excess of 200ft) at 9600 baud. Due to the cable length requirements, and unbalanced utilization of a twisted pair (one line for TX, and one line for RX), packet structure overhead had to be kept to a minimum. Under these restrictions, commands may still be issued 60 times per second. Dedicated industrial joystick controls and displays will eventually take the place of the host application once the design becomes stable.

Source Code

Both prettified and plain text versions are available.

The design is located in ptzlanc.phdl. All other files are libraries of devices.

Prettified Plain Text
connector.phdl connector.phdl
discrete.phdl discrete.phdl
ic.phdl ic.phdl
pinheader.phdl pinheader.phdl
ptzlanc.phdl ptzlanc.phdl <--Design located in these files
rcl.phdl rcl.phdl
switches.phdl switches.phdl


(Generated in EAGLE PCB)

Shown below is the layout for the PTZ LANC board. Both top and bottom copper and silkscreen layers are shown. Not shown are the internal power supply and ground copper layers.

Finished Board Results

Unstuffed Board Controlling a Brushless Motor

Top Component Side Bottom Component Side

All Wired Up Prototype Dev-board and Breadboard

Host Control Application

Shown below is a screen capture of the host controller application written in C# to communicate with the board. Under the command control tab, after filter parameters have been loaded, individual trajectory commands can be loaded into each axis, or simultaneous axes, and then executed. The internal signals register and status byte is displayed in a series of checkboxes.

Getting Started With PHDL

The best place to start is to visit our installation instructions which will help you get PHDL up and running on your machine. Then, be sure to visit the tutorial page.